Hardcaml Alternatives
[Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Hardcaml | 120 | 4 years ago | 14 | isc | OCaml | |||||
| [Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml | ||||||||||
| Icarus_verilog | 28 | 3 years ago | 1 | Verilog | ||||||
| This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum | ||||||||||
| My Verilog Examples | 22 | 2 years ago | mit | Verilog | ||||||
| A place to keep my synthesizable verilog examples. | ||||||||||
| Amber_samples | 17 | 13 years ago | Verilog | |||||||
| Verilog Osx | 15 | 4 years ago | Verilog | |||||||
| Barerbones OSX based Verilog simulation toolchain. | ||||||||||
| Fstdumper | 12 | a year ago | 4 | gpl-3.0 | C | |||||
| Verilog VPI module to dump FST (Fast Signal Trace) databases | ||||||||||
| Fliplot | 9 | 4 years ago | 11 | apache-2.0 | JavaScript | |||||
| HTML & Js based VCD viewer | ||||||||||
| Mawg | 8 | 4 years ago | other | Verilog | ||||||
| Modulation and Arbitrary Waveform Generator | ||||||||||
| Sap | 7 | 2 years ago | gpl-3.0 | Verilog | ||||||
| The SAP-1 in Verilog, and now as an ASIC! | ||||||||||
| Enigma_cryptol_bluespec_bsv | 7 | 8 years ago | Verilog | |||||||
| Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV | ||||||||||
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