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Search results for verilog eda
eda
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verilog
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43 search results found
Openroad
⭐
1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Fusesoc
⭐
1,065
Package manager and build abstraction tool for FPGA/ASIC development
Vtr Verilog To Routing
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925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Openfpga
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692
An Open-source FPGA IP Generator
Edalize
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573
An abstraction library for interfacing EDA tools
Opentimer
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368
A High-performance Timing Analysis Tool for VLSI Systems
Rggen
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261
Code generation tool for configuration and status registers
Openroad Flow Scripts
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233
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/la
Open Register Design Tool
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169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Vsdflow
⭐
121
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Ope
Fault
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102
A complete open-source design-for-testing (DFT) Solution
Ice Chips Verilog
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99
IceChips is a library of all common discrete logic devices in Verilog
Openlane2
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99
The next generation of OpenLane, rewritten from scratch with a modular architecture
Yosys F4pga Plugins
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81
Plugins for Yosys developed as part of the F4PGA project.
Circuitgraph
⭐
74
Tools for working with circuits as graphs in python
Spydrnet
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66
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Sv2chisel
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59
(System)Verilog to Chisel translator
Fan_atpg
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51
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Peakrdl
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48
Control and status register code generator toolchain
Vlsistuff
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42
ideas and eda software for vlsi design
Naja
⭐
34
Structural Netlist API (and more) for EDA post synthesis flow development
Xeda
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30
Cross EDA Abstraction and Automation
Ophidian
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29
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Parser Verilog
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24
A Standalone Structural Verilog Parser
Naja Verilog
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18
A standalone structural (gate-level) verilog parser
Globalfoundries Pdk Libs Gf180mcu_fd_sc_mcu7t5v0
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16
7 track standard cells for GF180MCU provided by GlobalFoundries.
Vsdmixedsignalflow
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16
This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
Datc_robust_design_flow
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15
DATC Robust Design Flow.
Globalfoundries Pdk Libs Gf180mcu_fd_sc_mcu9t5v0
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14
9 track standard cells for GF180MCU provided by GlobalFoundries.
Rdf 2019
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14
DATC RDF
Study Materials
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12
Globalfoundries Pdk Ip Gf180mcu_fd_ip_sram
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12
SRAM macros created for the GF180MCU provided by GlobalFoundries.
Globalfoundries Pdk Libs Gf180mcu_fd_io
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11
IO and periphery cells for the GF180MCU provided by GlobalFoundries.
Pyedaa.projectmodel
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10
An abstract model of EDA tool projects.
Awesome Eda
⭐
9
Phi
⭐
7
Hardware description language that tries not to suck
Libcircuit
⭐
6
libCircuit is a C++ Library for EDA software development
Edapack
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6
Provides a packaged collection of open source EDA tools
Sky130_cds
⭐
6
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Netlist
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5
generic NetList data structure for VLSI
Riscv Isa Ci
⭐
5
CI/CD for RISC-V Cores
Eda Tools
⭐
5
Verilog Gate-Level Studio
Go.debug
⭐
5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
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1-43 of 43 search results
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