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Search results for fpga synthesis
fpga
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synthesis
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48 search results found
Vtr Verilog To Routing
⭐
925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Edalize
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573
An abstraction library for interfacing EDA tools
Pipelinec
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519
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Leflow
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329
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Poc
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324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
F4pga Arch Defs
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245
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Livehd
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192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Panda Bambu
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192
PandA-bambu public repository
Async_fifo
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173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Hls_tutorial_examples
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107
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Karuta
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87
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Rt
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71
A Full Hardware Real-Time Ray-Tracer
Json For Vhdl
⭐
61
A JSON library implemented in VHDL.
Pycoram
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42
Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
Frix
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32
IBM PC Compatible SoC for a commercially available FPGA board
Xeda
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30
Cross EDA Abstraction and Automation
My Verilog Examples
⭐
22
A place to keep my synthesizable verilog examples.
Design And Asic Implementation Of 32 Point Fft Processor
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20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
Hwthls
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20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Poc Examples
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19
This repository contains synthesizable examples which use the PoC-Library.
Eda Collection
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19
Hls Cnn
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19
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
Rudolv
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19
RISC-V processor
Chiptools
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18
ChipTools is a utility to automate FPGA build and verification
Picoblaze Library
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18
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Hls_fpga_nes
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14
An FPGA NES emulator designed by a high level synthesis (HLS)
Tiny Tpu
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14
Small-scale Tensor Processing Unit built on an FPGA
Opennas
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12
OpenN@S: Open-source software to NAS automatic VHDL code generation
Light52
⭐
11
Yet another free 8051 FPGA core
C Ll Verilog
⭐
10
An LLVM based mini-C to Verilog High-level Synthesis tool
Bpm Gw
⭐
10
Repository containing the gateware for the Beam Position Monitor project
Cis371
⭐
10
repo for CIS 371 Spring 2018
Comet
⭐
10
RISC-V ISA based 32-bit processor written in HLS
Hls_ldpc_dec
⭐
9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Awesome Eda
⭐
9
S Link
⭐
8
An Open Source Link Protocol and Controller
Yosys Bluespec
⭐
8
Yosys plugin for synthesis of Bluespec code
Multiported Ram
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8
Modular Multi-ported SRAM-based Memory
Bwa Mem Sw
⭐
8
Vdf Fpga Round2 Results
⭐
7
Hls_for_cnn
⭐
7
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Rc4 Prbs
⭐
7
A Verilog open-source implementation of a RC4 encryption algorigthm using a pseudorandom binary sequence (PRBS) for FPGA synthesis.
Chai Fpga
⭐
6
Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
Fpga Brainfuck
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6
Brainfuck CPU for FPGA
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Digilite_zl
⭐
5
DigiLiteZL FPGA
Yaaes
⭐
5
Yet Another AES implementation in hardware.
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1-48 of 48 search results
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