Light52
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vtr Verilog To Routing | 925 | 3 months ago | 447 | other | C++ | |||||
| Verilog to Routing -- Open Source CAD Flow for FPGA Research | ||||||||||
| Edalize | 573 |  | 2 | 3 | 3 months ago | 24 | December 08, 2023 | 91 | bsd-2-clause | Python |
| An abstraction library for interfacing EDA tools | ||||||||||
| Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
| Leflow | 329 | 4 years ago | 1 | other | Verilog | |||||
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks | ||||||||||
| Poc | 324 | 4 years ago | 31 | other | VHDL | |||||
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany | ||||||||||
| F4pga Arch Defs | 245 | a month ago | 366 | isc | Jupyter Notebook | |||||
| FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. | ||||||||||
| Livehd | 192 | 3 months ago | 4 | June 06, 2018 | 11 | other | Verilog | |||
| Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation | ||||||||||
| Panda Bambu | 192 | 3 months ago | 8 | gpl-3.0 | C++ | |||||
| PandA-bambu public repository | ||||||||||
| Async_fifo | 173 | a year ago | other | Verilog | ||||||
| A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog | ||||||||||
| Logic | 121 | 4 years ago | apache-2.0 | SystemVerilog | ||||||
| CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. | ||||||||||
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