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19 search results found

Openlane ⭐ 1,148

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Opentimer ⭐ 368

A High-performance Timing Analysis Tool for VLSI Systems

A modern and open-source cross-platform software for chips reverse engineering.

Open source software for chip reverse engineering.

Standard Cell Library based Memory Compiler using FF/Latch cells

Openlane2 ⭐ 99

The next generation of OpenLane, rewritten from scratch with a modular architecture

Vlsiffra ⭐ 89

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Fan_atpg ⭐ 51

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

phoeniX RISC-V Processor

Crash_course_for_new_members ⭐ 26

Deep Learning & VLSI Crash Course for New Members

Atalanta ⭐ 22

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Delta Sigma Dac Verilog ⭐ 14

Delta Sigma DAC FPGA

Rdf 2019 ⭐ 14

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Cdsasync ⭐ 10

cdsAsync: An Asynchronous VLSI Toolset & Schematic Library

Mastering Fpgasic Book ⭐ 8

📖 Mastering FPGASIC Book

30 Days Of Verilog ⭐ 7

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

Sky130_cds ⭐ 6

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

generic NetList data structure for VLSI

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