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44 search results found
Openlane
⭐
1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Dreamplace
⭐
560
Deep learning toolkit-enabled VLSI placement
Opentimer
⭐
368
A High-performance Timing Analysis Tool for VLSI Systems
Poc
⭐
324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Degate
⭐
212
A modern and open-source cross-platform software for chips reverse engineering.
Degate
⭐
151
Open source software for chip reverse engineering.
Vlsi Fundamentals Education Kit
⭐
122
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Dffram
⭐
101
Standard Cell Library based Memory Compiler using FF/Latch cells
Openlane2
⭐
99
The next generation of OpenLane, rewritten from scratch with a modular architecture
Vlsiffra
⭐
89
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Act
⭐
88
ACT hardware description language and core tools.
Gds2para
⭐
76
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Eesim
⭐
73
A browser-based SPICE circuit simulator
Fan_atpg
⭐
51
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Phoenix
⭐
34
phoeniX RISC-V Processor
Parser Spef
⭐
29
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Crash_course_for_new_members
⭐
26
Deep Learning & VLSI Crash Course for New Members
Atalanta
⭐
22
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Qt_painter
⭐
22
CAD framework tool on top of Qt
Nthu Route
⭐
21
VLSI EDA Global Router
Padring
⭐
19
A padring generator for ASICs
Amc
⭐
19
AMC: Asynchronous Memory Compiler
Ogre
⭐
19
Global Router Built for ICCAD Contest 2019
Ml2tikz
⭐
16
maskLayout to tikzpicture converter for Cadence Virtuoso
Magic_vlsi_examples
⭐
16
Some simple examples for the Magic VLSI physical chip layout tool.
Delta Sigma Dac Verilog
⭐
14
Delta Sigma DAC FPGA
Gatery
⭐
14
Gatery, a library for circuit design.
Actflow
⭐
14
Top-level repository for the ACT EDA flow
16 Bit Hdlc Using Vhdl
⭐
14
High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
Rdf 2019
⭐
14
DATC RDF
Doug
⭐
12
Doug is a WIP semi-automated to full manual VLSI Analog and Mixed Signal CAD design tool built with Bevy and Layout21
Mida
⭐
11
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Digital Hardware Modelling
⭐
11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Electrical And Electronic Engineering Course Materials
⭐
10
Electrical And Electronic Engineering Course Materials
Cdsasync
⭐
10
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
Mastering Fpgasic Book
⭐
8
📖 Mastering FPGASIC Book
Sch2tikz
⭐
8
schematic to tikzpicture converter for Cadence Virtuoso
Anubis
⭐
8
The ANUBIS benchmark suite for Incremental Synthesis
30 Days Of Verilog
⭐
7
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
Ravenna
⭐
7
32-bit RISC-V microcontroller
Sky130_cds
⭐
6
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Netlist
⭐
5
generic NetList data structure for VLSI
Pyqt_genetic_algo
⭐
5
genetic algorithm usage for routing optimization ( pyqt )
Pydesignflow
⭐
5
Micro-Framework for FPGA / VLSI Design Flow in Python
1-44 of 44 search results
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