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Search results for verilog uvm
uvm
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verilog
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15 search results found
Cocotb
⭐
1,583
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Surelog
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325
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Rggen
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261
Code generation tool for configuration and status registers
Hwt
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189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Open Register Design Tool
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169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Awesome Dv
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76
Awesome ASIC design verification
Peakrdl
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48
Control and status register code generator toolchain
Async_fifo
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41
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Ahb To Apb Bridge Verification
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34
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
Rggen
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17
This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
Rggen Sample Testbench
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14
Int_fp_mac
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12
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Axi_to_spi
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7
Designing means to communicate as an SPI master, being a part of AXI interface
Go.debug
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5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
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1-15 of 15 search results
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