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Search results for verilog formal verification
formal-verification
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verilog
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13 search results found
Awesome Open Hardware Verification
⭐
353
A List of Free and Open Source Hardware Verification Tools and Frameworks
Xcrypto
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80
XCrypto: a cryptographic ISE for RISC-V
Awesome Dv
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76
Awesome ASIC design verification
Avr
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47
Reads a state transition system and performs property checking
Cosa
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35
CoreIR Symbolic Analyzer
Risc V
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29
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
Formal_hw_verification
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23
Trying to verify Verilog/VHDL designs with formal methods and tools
Scarv Cpu
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18
SCARV: a side-channel hardened RISC-V platform
Hardware
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18
Verilog development and verification project for HOL4
Croyde Riscv
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10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Little Cpu
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8
Little cpu in verilog.
Xprova
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6
Formal verification engine for Verilog with built-in support for simulating flip-flop metastability
Edapack
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6
Provides a packaged collection of open source EDA tools
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1-13 of 13 search results
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