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Search results for verilog fpga

776 search results found

Usb_cdc ⭐ 131

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Usb3_pipe ⭐ 126

USB3 PIPE interface for Xilinx 7-Series

A Video display simulator

Image Processing ⭐ 123

Image Processing Toolbox in Verilog using Basys3 FPGA

Corescore ⭐ 122

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Fpga Can ⭐ 121

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Dspfilters ⭐ 119

A collection of demonstration digital filters

Ice40_ultraplus_examples ⭐ 115

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Fpga_based_cnn ⭐ 113

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Simplevout ⭐ 112

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

Tinytpu ⭐ 111

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Cnn Fpga ⭐ 109

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Haasoscope ⭐ 107

Docs, design, firmware, and software for the Haasoscope

Icestation 32 ⭐ 107

Compact FPGA game console

Tang_e203_mini ⭐ 103

LicheeTang 蜂鸟E203 Core

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca

Ice Chips Verilog ⭐ 99

IceChips is a library of all common discrete logic devices in Verilog

Mobilenet In Fpga ⭐ 96

Generator of verilog description for FPGA MobileNet implementation

Panologic G2 ⭐ 96

Pano Logic G2 Reverse Engineering Project

Fpga Application Development And Simulation ⭐ 96

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Ice40_examples ⭐ 94

Public examples of ICE40 HX8K examples using Icestorm

SD-Card controller, using a SPI interface that is (optionally) shared

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Kamikaze ⭐ 88

Light-weight RISC-V RV32IMC microcontroller core.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

The Task Parallel System Composer (TaPaSCo)

Neogeofpga Sim ⭐ 87

Simulation only cartridge NeoGeo hardware definition

Haskell library for hardware description

Lispmicrocontroller ⭐ 85

A microcontroller that natively executes a simple LISP dialect

Fpga Ddr Sdram ⭐ 83

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Vt52 Fpga ⭐ 83

A collection of phase locked loop (PLL) related projects

Yosys F4pga Plugins ⭐ 81

Plugins for Yosys developed as part of the F4PGA project.

Fpga Rocket Chip ⭐ 79

Wrapper for Rocket-Chip on FPGAs

Cnn_for_slr ⭐ 79

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

Openarty ⭐ 77

An Open Source configuration of the Arty platform

Yet Another RISC-V Implementation

Fpga Cnn ⭐ 76

FPGA implementation of Cellular Neural Network (CNN)

Limesdr Usb_gw ⭐ 76

Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

The second place winner for DAC-SDC 2020

Xilinx Serial Miner ⭐ 75

Bitcoin miner for Xilinx FPGAs

Lattice iCE40 FPGA experiments - Work in progress

Mipsfpga Plus ⭐ 74

MIPSfpga+ allows loading programs via UART and has a switchable clock

YM2151 clone in verilog. FPGA proven.

Implementation Nintendo's GameBoy console on an FPGA

Fpga Nfc ⭐ 73

Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Keyboard ⭐ 72

客制化机械键盘——从0开始全套资料

A reimplementation of a tiny stack CPU

A Full Hardware Real-Time Ray-Tracer

Core_ddr3_controller ⭐ 69

A DDR3 memory controller in Verilog for various FPGAs

Fpga Sdfake ⭐ 69

Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。

A series of CORDIC related projects

A wishbone controlled scope for FPGA's

Open Nic Shell ⭐ 67

AMD OpenNIC Shell includes the HDL source files

Spydrnet ⭐ 66

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Simulating Verilog designs on a microcontroller

Filament ⭐ 66

Fearless hardware design

FPGA Based Apollo Guidance Computer

Antikernel ⭐ 65

The Antikernel operating system project

C5soc_opencl ⭐ 65

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

Display_controller ⭐ 64

FPGA display controller with support for VGA, DVI, and HDMI.

Tinyfpga_bx_usbserial ⭐ 63

USB Serial on the TinyFPGA BX

Parallel Array of Simple Cores. Multicore processor.

Sega System For Fpga ⭐ 61

FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.

Arduino compatible – Cortex M4F & FPGA Development Board

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

Cnn_open ⭐ 60

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Common framework for MiST(er), PocketFPGA, SiDi, NeptUNO (mc/mc2) core development. With special focus on arcade cores.

Oc Accel ⭐ 58

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

Fpga Odysseus ⭐ 58

FPGA Odysseus with ULX3S

open-source logic analyzer for FPGAs

Fpga Png Decoder ⭐ 57

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。

Verilog Uart ⭐ 56

3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器

Issie - an intuitive cross-platform hardware design application. https://tomcl.github.io/issie

Fpga Mpeg2 Encoder ⭐ 56

FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Reindeer ⭐ 56

PulseRain Reindeer - RISCV RV32I[M] Soft CPU

Fpga Md5 Cracker ⭐ 55

A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.

Dslogic Hdl ⭐ 55

An open source FPGA design for DSLogic

Riscy Soc ⭐ 54

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Fpga Sata Hba ⭐ 54

A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

Openfpga Pong ⭐ 53

FPGA Pong implementation, specifically for the Analogue Pocket

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Uniplug Fpga ⭐ 53

体积小、低成本、易用、扩展性强的 FPGA 核心板

Upduino v2 with the ice40 up5k FPGA demos

Vidorfpga ⭐ 53

repository for Vidor FPGA IP blocks and projects

Timetoexplore ⭐ 52

Source code to accompany https://timetoexplore.net

FPGA based transmitter

Fpga Sdcard Reader Spi ⭐ 52

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

Netv Fpga ⭐ 52

verilog FPGA code for NeTV

Control and Status Register map generator for HDL projects

Icebreaker Workshop ⭐ 52

iCEBreaker Workshop

Fpga Rmii Smii ⭐ 51

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等

Fpga Gzip Compressor ⭐ 51

FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于 FPGA 的流式 GZIP 压缩器。输入原始数据，输出标准的 GZIP 格式，即常见的 .gz / .tar.gz 文件的格式。

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