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Search results for verilog waveform
verilog
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waveform
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21 search results found
Hardcaml
⭐
120
[Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml
Tree Core Ide
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56
The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Icarus_verilog
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28
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
Jtag_vpi
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28
TCP/IP controlled VPI JTAG Interface.
My Verilog Examples
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22
A place to keep my synthesizable verilog examples.
Amber_samples
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17
Verilog Osx
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15
Barerbones OSX based Verilog simulation toolchain.
Ofdm
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14
Chisel Things for OFDM
Waveview
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14
Digital Waveform Viewer
Fstdumper
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12
Verilog VPI module to dump FST (Fast Signal Trace) databases
Vcdvis
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11
VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.
Softmax
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10
Verilog implementation of Softmax function
Fliplot
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9
HTML & Js based VCD viewer
Python To Verilog
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9
Generate a Verilog Source file and testbench file for a given Moore FSM
Mawg
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8
Modulation and Arbitrary Waveform Generator
Sap
⭐
7
The SAP-1 in Verilog, and now as an ASIC!
Enigma_cryptol_bluespec_bsv
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7
Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
Ax301
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6
AX301
Gstmcu
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6
Simulation model of the Atari STE GSTMCU
Wavedisp
⭐
5
Python classes to create agnostic wave files for HDL simulator viewer
Dma_axi
⭐
5
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1-21 of 21 search results
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