Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Digital | 3,476 | 5 months ago | 87 | gpl-3.0 | Java | |||||
A digital logic designer and circuit simulator. | ||||||||||
8 Bits Risc Cpu Verilog | 53 | 5 years ago | n,ull | mit | Verilog | |||||
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。 | ||||||||||
Hrm Cpu | 43 | 3 years ago | 15 | gpl-3.0 | Verilog | |||||
Human Resource Machine - CPU Design #HRM | ||||||||||
Ddlm | 42 | 9 months ago | 1 | mit | Verilog | |||||
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула) | ||||||||||
Aes | 20 | 2 years ago | 1 | mit | Verilog | |||||
Advanced encryption standard implementation in verilog. | ||||||||||
Fizzim2 | 9 | 2 years ago | 1 | Java | ||||||
FSM (Finite State Machine) tools for Verilog HDL. | ||||||||||
Python To Verilog | 9 | 12 years ago | other | Python | ||||||
Generate a Verilog Source file and testbench file for a given Moore FSM | ||||||||||
Fpga Spi Flash | 8 | 4 years ago | mit | VHDL | ||||||
Various projects of SPI loader module for xilinx fpga | ||||||||||
Tizzy | 6 | 13 years ago | 1 | other | Python | |||||
Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python | ||||||||||
Applied_digital_logic_exercises_using_fpgas | 6 | 2 years ago | Verilog | |||||||
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick. |