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Search results for verilog vhdl

137 search results found

VHDL Library for implementing common DSP functionality.

Free Hdl License ⭐ 9

Working space for free software licenses for hardware description language (e.g. VHDL, Verilog, Bluespec) projects

Teroshdl Documenter Demo ⭐ 9

This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

Hdlgen Chatgpt ⭐ 9

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Gatemate_experiments ⭐ 9

Experiments with Cologne Chip's GateMate FPGA architecture

Verilog_calculator_matrix_multiplication ⭐ 8

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Rocket Chip ⭐ 8

Fpga Spi Flash ⭐ 8

Various projects of SPI loader module for xilinx fpga

Mastering Fpgasic Book ⭐ 8

📖 Mastering FPGASIC Book

Oram_fpga ⭐ 8

FPGA related files for ORAM

A Modestly Exhaustive dLx Architecture - RISC microprocessor - VHDL implementation - DLX ISA

Sphinx Hwt ⭐ 7

Sphinx extension for visual documentation of hardware written in HWT

Burningrouter ⭐ 7

Project of Computer Network & Computer Organization, Tsinghua University, 2019 autumn; A hardware router (hardware part)

PCB to plug FPGA softcore CPU into 68060 microprocessor socket

Ipcorepackager ⭐ 6

Scriptable IP-Core generator

SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs.

Rtl Coding ⭐ 6

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Xilinx Bitstream Format Library. Easily read .bit files from C programs.

Provides a packaged collection of open source EDA tools

SystemVerilog & Verilog Module I/O parser and printer

Python Frontend For VHDL And Verilog

Blackman_harris_win ⭐ 5

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

Snake Verilog ⭐ 5

This program is written in verilog .

Hdl_plugin ⭐ 5

Generate vhdl/verilog testbench file for vhdl files.

Describing RTL circuit in Ruby

Lzw_verilog ⭐ 5

LZW Compressoion algorithm in verilog

Basys3 Pong ⭐ 5

BASYS 3 - PONG GAME

Python classes to create agnostic wave files for HDL simulator viewer

Meowrouter Top ⭐ 5

Top for MeowRouter

Verilog_jump ⭐ 5

An FPGA version of the WeChat Jump(跳一跳) game using Nexys4 DDR and its onboard accelerometer.

Digiblock ⭐ 5

An experimental package manager and development tool for Hardware Description Languages (HDL).

Verdi like, verilog code signal trace and show hierarchy script

Sublimelinter Contrib Xsim ⭐ 5

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

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