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Search results for verilog fpga

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Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Evoapproxlib ⭐ 28

Library of approximate arithmetic circuits

Verilog Caches ⭐ 28

Various caches written in Verilog-HDL

Sdram Controller ⭐ 27

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Xilinx Risc V ⭐ 26

Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.

mirror of https://git.elphel.com/Elphel/x393

Vtr Verilog To Routing ⭐ 26

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

Openfpga Tutorials ⭐ 26

A collection of tutorials and resources for the openFPGA platform.

Tiny MIPS for Terasic DE0

Fpga_qpsk Modem ⭐ 26

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Ddk Fpga ⭐ 25

FPGA HDL Sources.

i8080 precise replica in Verilog, based on reverse engineering of real die

Displayport ⭐ 25

DisplayPort IP-core

A simple implementation of a UART modem in Verilog.

Cnn_fpga ⭐ 25

verilog CNN generator for FPGA

Arcade Tmnt_mister ⭐ 25

Konami's Teenage Mutant Ninja Turtles for the MiSTer FPGA platform

FPGA Based lock in amplifier

First Fpga Pcb ⭐ 25

FPGA dev board based on Lattice iCE40 8k

Hdlconvertorast ⭐ 25

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

'PERIDOT' - Simple & Compact FPGA board

Icebreaker Candy ⭐ 24

Eye candy from an iCEBreaker FPGA and a 64×64 LED panel

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

Pergola_projects ⭐ 24

My pergola FPGA projects

Hwac_object_tracker ⭐ 24

FPGA accelerated TinyYOLO v2 object detection neural network

Fpga_threelevelstorage ⭐ 23

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Neochips ⭐ 23

Replacement "chips" for NeoGeo systems

Riscv Soc Cores ⭐ 23

Hackaday_supercon_2019_logic_noise_fpga_workshop ⭐ 23

Hackaday Supercon 2019 Logic Noise Badge Workshop

Spaceinvadersfpgagame ⭐ 23

Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board

mirror of https://git.elphel.com/Elphel/eddr3

Arm9 Compatible Soft Cpu Core ⭐ 23

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Scoreboard Wtimer ⭐ 23

Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.

Fpga Game Design ⭐ 23

Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Fpga_ultrasound ⭐ 22

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

Bapi Rv32i ⭐ 22

A extremely size-optimized RV32I soft processor for FPGA.

VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)

Uhd Fairwaves ⭐ 22

Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.

Fpga Stereo Camera Basys3 ⭐ 22

Integration of two camera modules to Basys 3 FPGA

Stepfpga Mxo2core ⭐ 22

The codes accompanied with STEPFPGA tutorial book

Gameduino Fpga Mods ⭐ 22

Mods of the FPGA code from @jamesbowman's Gameduino file repository

Fpga Virtual Graf ⭐ 21

Lvds 7 To 1 Serializer ⭐ 21

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Thunderclap Fpga Arria10 ⭐ 21

Thunderclap hardware for Intel Arria 10 FPGA

Hps2fpgamapping ⭐ 21

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Pong game on an FPGA in Verilog.

Sm3_core ⭐ 21

Sift Implementation In Verilog ⭐ 21

Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations

Openhbmc ⭐ 21

Open-source high performance AXI4-based HyperRAM memory controller

Open source ISS and logic RISC-V 32 bit project

Lemoncore ⭐ 20

Simple RISC-V processor for FPGAs 🍋 🤖

Transient Array Radio Telescope

Vision Fpga Som ⭐ 20

tinyVision.ai Vision & Sensor FPGA System on Module

Fpga Docker ⭐ 20

Tools for running FPGA vendor toolchains with Docker

Pythonuberhdl ⭐ 20

Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

Paas_v1.0 ⭐ 20

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

IEEE 754 floating point library in system-verilog and vhdl

A wishbone controlled FM transmitter hack

Home Brew Computer ⭐ 19

SystemOT, yet another home brew cpu.

Booth_multipliers ⭐ 19

Parameterized Booth Multiplier in Verilog 2001

De10nano_vgahdmi_chip ⭐ 19

Test for video output using the ADV7513 chip on a de10 nano board

Verilog Fpga ⭐ 19

Many peripherals in Verilog ready to use

Verilog implementation of the SHA-512 hash function.

Rtcclock ⭐ 19

A Real Time Clock core for FPGA's

No2muacm ⭐ 18

Drop In USB CDC ACM core for iCE40 FPGA

CIS 501: Computer Architecture Fall 2019

Icestick Lpc Tpm Sniffer ⭐ 18

FGBA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit

Picoblaze Library ⭐ 18

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

An open source hardware engine for Open vSwitch on FPGA

Propeller_1_design ⭐ 18

Propeller 1 design and example files to be run on FPGA boards.

Enigmafpga ⭐ 18

An infrastructure for inline acceleration of network applications

A self-hosting Forth for J1-style CPUs

Virtio implementation in SystemVerilog

A C64 SID Chip recreation in FPGA

Spartan Mini Nes ⭐ 18

An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.

The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs.

Biggateboy ⭐ 18

WIP Big FPGA Gameboy

Handwritten Digit Recognition Painter ⭐ 18

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

Fpgaminer Vanitygen ⭐ 17

Open Source Bitcoin Vanity Address Generation on FPGAs

Fpga Bpf ⭐ 17

A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

Nyan Keys Ice40hx4k Bitstream ⭐ 17

A 60% Low Latency FPGA Mech Keyboard

Hdmi To Fpga To Apa102 Pixels ⭐ 17

Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.

Fpga_gameboy_watch ⭐ 17

Full gameboy and gameboy color Verilog Implenentation

Verilog Mini Demo ⭐ 17

Verilog极简教程

Async Karin ⭐ 17

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

Bgbtech_btsr1arch ⭐ 17

BtSR1 and BJX2 ISA / CPU Architecture

Upduino Ov7670 Camera ⭐ 17

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

Fpga Ov2640 ⭐ 17

This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.

Insider System ⭐ 17

An FPGA-based full-stack in-storage computing system.

FPGA USB 1.1 Low-Speed Implementation

Fpga Hash Table ⭐ 16

Simple hash table on Verilog (SystemVerilog)

Nvdla Wrapper ⭐ 16

Wraps the NVDLA project for Chipyard integration

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