Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Uhd | 869 | 3 | 4 months ago | 11 | September 14, 2022 | 93 | other | Verilog | ||
The USRP™ Hardware Driver Repository | ||||||||||
Sdr | 56 | 3 months ago | Verilog | |||||||
A basic Soft(Gate)ware Defined Radio architecture | ||||||||||
Gr Verilog | 29 | 5 years ago | 1 | gpl-3.0 | C++ | |||||
This is an OOT module for GNU Radio integrating verilog simulation feature | ||||||||||
Tart | 20 | 2 | 3 | 2 years ago | 25 | December 02, 2023 | 34 | lgpl-3.0 | Verilog | |
Transient Array Radio Telescope | ||||||||||
Fpga Sdrlib | 13 | 11 years ago | mit | Python | ||||||
Verilog modules for software-defined radio. | ||||||||||
Radio 86rk Wxeda | 12 | 9 years ago | bsd-2-clause | Verilog | ||||||
Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board | ||||||||||
Fpga Pm Radio | 9 | 7 years ago | Verilog | |||||||
Implement Phase Modulation Radio Transmitter in FPGA Altera MAX10, with Marsohod3bis FPGA board. | ||||||||||
Drfm | 5 | 2 years ago | Verilog | |||||||
Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System" | ||||||||||
Freerider | 5 | 7 years ago | Verilog | |||||||