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141 search results found
Hdlgen Chatgpt
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9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
Hls_ldpc_dec
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9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Manta
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8
An In-Situ Debugging Tool for Programmable Hardware
Basic Hdl Template
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8
A simple template for simple FPGA projects (mostly Verilog HDL and Xilinx Toolchain)
Lane Detection With Implementation On Fpga
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8
Realization of Lane Detection on CPU and implementation on FPGA using SDSOC and VIVADO. Key terms for used softwares: C++, OpenCV, xfOpenCV, Verilog, Xilinx, Vivado, SdSoC.
Mastering Fpgasic Book
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8
📖 Mastering FPGASIC Book
Axicores
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8
AXI4-Compatible Verilog Cores, along with some helper modules.
Sigma
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8
Fpga Spi Flash
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8
Various projects of SPI loader module for xilinx fpga
Gameboy
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8
18-545 Fighting Meerkats
Oram_fpga
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8
FPGA related files for ORAM
Verilog_calculator_matrix_multiplication
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8
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
Cpuonfpga
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8
It's a basic computer designed using VERILOG on XILINX FPGA architecture.
Fluent10g
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8
Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
Pymtl Tut Hls
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8
Tutorial for integrating PyMTL and Vivado HLS
Pciebench Netfpga
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8
pcie-bench code for NetFPGA/VCU709 cards
Cstron
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7
FPGA-based CSTN monitor
Sitcp_netlist_for_kintex7
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7
Verilog Spi
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7
This is a SPI Master Module Written in Verilog
Core_sdram_axi4
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7
SDRAM controller with AXI4 interface
Fpga Camera Mipi Dvp Verilog
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7
FPGA Camera Parallel & MIPI Verilog
Openxc7 Tetrisaraj
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7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
Mandelbrot
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6
A Verilog based Fractal Set Generator for the Xilinx Artix 7
Ncore
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6
A RISCV processor in system verilog
Sparkfun Rgb Bar Graph
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6
Libxbf
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6
Xilinx Bitstream Format Library. Easily read .bit files from C programs.
Hdu_co_guide
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6
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
Desrtfpga
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6
DES Rainbow Table FPGA Code
Viterbi Decoder In Verilog
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6
An efficient implementation of the Viterbi decoding algorithm in Verilog
Zynq 7000 Dpu Trd
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6
Zynq-7000 DPU TRD
Ht Deflate Fpga
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6
Arty Cm0 Designstart
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5
A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
Fsearch
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5
FastSearch is a project intended to increase the speed of string searching by using the FPGA technology
Arty_xjtag
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5
Xilinx JTAG Toolchain on Digilent Arty board
Verilog Matrix Multiplier
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5
Final Project for Digital Systems Design Course, Fall 2020
Riscv_sbc
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5
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Mips Cpu
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5
Xilinx Project for MIPS CPU
Gost 28147 89
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5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Rautanoppa
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5
Hardware random number generator for FPGAs
C16
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5
C16/Plus4 core
Genx
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5
Script for Xilinx/Vivado/Zynq/krtkl-snickerdoodle developers. Automates generation / maintenance of AXI glue, XDC files, lookup ROMs, etc.
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101-141 of 141 search results
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