Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for verilog tcl
tcl
x
verilog
x
24 search results found
Basic_verilog
⭐
1,333
Must-have verilog systemverilog modules
Openroad
⭐
1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Openroad Flow Scripts
⭐
233
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/la
Vsdflow
⭐
121
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Ope
Fpgamake
⭐
78
Generates Makefiles to synthesize, place, and route verilog using Vivado
Skrskr
⭐
76
The second place winner for DAC-SDC 2020
Openphysyn
⭐
46
EDA physical synthesis optimization kit
Ddlm
⭐
42
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Custom_part_data_files
⭐
28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
Cis501
⭐
18
CIS 501: Computer Architecture Fall 2019
Ece1373_2016_hft_on_fpga
⭐
16
High Frequency Trading using Vivado HLS
Asynchronous Verilog Synthesiser
⭐
14
Synthesiser for Asynchronous Verilog Language
Study Materials
⭐
12
Yosys Tcl Ui Report
⭐
12
5 Day TCL begginer to advanced training workshop by VSD
Nldb
⭐
10
Verilog netlist parser/database (derived from http://nldb.sourceforge.net)
32 Point Fft Verilog Design Based Dit Butterfly Algorithm
⭐
10
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
Icglue
⭐
9
A Tcl-Library for scripted HDL generation
Source_to_inst
⭐
9
This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
Pymtl Tut Hls
⭐
8
Tutorial for integrating PyMTL and Vivado HLS
Sky130rhbdlib
⭐
7
Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
Verilog Spi
⭐
7
This is a SPI Master Module Written in Verilog
Hdu_co_guide
⭐
6
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
F4pga Xc Fasm2bels
⭐
6
Library to convert a FASM file into BELs importable into Vivado.
Sky130_cds
⭐
6
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Related Searches
Verilog Fpga (1,343)
Cpu Verilog (330)
Python Verilog (267)
Verilog Xilinx (265)
C Tcl (260)
Verilog Vhdl (249)
Verilog Systemverilog (230)
Verilog Rtl (217)
Python Tcl (214)
C Plus Plus Verilog (187)
1-24 of 24 search results
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.