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Search results for verilog modelsim

modelsim x
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10 search results found
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
Vscode Verilog Hdl Support ⭐ 266
HDL support for VS Code
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Fpga Application Development And Simulation ⭐ 96
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Vim Hdl ⭐ 53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Ddlm ⭐ 42
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Hardware Implementation Of The Canny Edge Detection Algorithm ⭐ 9
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
Verilog Matrix Multiplier ⭐ 5
Final Project for Digital Systems Design Course, Fall 2020
Wavedisp ⭐ 5
Python classes to create agnostic wave files for HDL simulator viewer
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