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ddr3
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4 search results found
Brianhg Ddr3 Controller
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34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Ddr3 Controller
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32
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Eddr3
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23
mirror of https://git.elphel.com/Elphel/eddr3
Riscv_sbc
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5
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
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