Awesome Open Source

Programming Languages

Search results for verilog fpga

776 search results found

Up5k_basic ⭐ 50

A small 6502 system with MS BASIC in ROM

Web-based HDL diagramming tool

Asic Design Roadmap ⭐ 49

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Icez0mb1e ⭐ 49

FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC

Engine V ⭐ 49

SoftCPU/SoC engine-V

Cnn Accelerator Vlsi ⭐ 48

Convolutional accelerator kernel, target ASIC & FPGA

Minimig Mist ⭐ 48

Minimig for the MiST board

Airisc_core_complex ⭐ 48

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.

Fpga Lzma Compressor ⭐ 48

FPGA-based LZMA compressor. For generic lossless data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Control and status register code generator toolchain

Limesdr Mini_gw ⭐ 47

LimeSDR-Mini board FPGA project

Electron ⭐ 46

A mixed signal netlist language (pre-alpha)

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

Getting Started ⭐ 46

List of ideas for getting started with TimVideos projects

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A simple GPU on a TinyFPGA BX

Original FPGA platform

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

Litex Cnc ⭐ 44

Generic CNC firmware and driver for FPGA cards which are supported by LiteX

Verilog Sha Family ⭐ 43

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

Human Resource Machine - CPU Design #HRM

Openfpga Arduboy ⭐ 43

Arduboy for Analogue Pocket

Sphinxcontrib Hdl Diagrams ⭐ 43

Sphinx Extension which generates various types of diagrams from Verilog code.

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

Fixed Floating Point Adder Multiplier ⭐ 42

16-bit Adder Multiplier hardware on Digilent Basys 3

Interpolation ⭐ 42

Digital Interpolation Techniques Applied to Digital Signal Processing

Eveide_light ⭐ 41

A lightweight IDE that supports verilog simulation and RISC-V code compilation

Super Miyamoto Sprint ⭐ 41

Homebrew game for homebrew FPGA game console

Digital Servo ⭐ 41

NIST digital servo: an FPGA based fast digital feedback controller

Verilog Systemverilog Guide ⭐ 41

Verilog/SystemVerilog Guide

Test of the USB3 IP Core from Daisho on a Xilinx device

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Usb_sniffer ⭐ 40

High Speed USB 2.0 capture device based on miniSpartan6+

A QUbic Programming LAnguage

A port of Linux to the OWON SDS7102 scope

Hyperram ⭐ 39

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

No2bootloader ⭐ 39

USB DFU bootloader gateware / firmware for FPGAs

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

Nybbleforth ⭐ 38

Stack machine with 4-bit instructions

Fpga101 Workshop ⭐ 38

FPGA 101 - Workshop materials

Verilog module compatible with Yamaha OPL chips

IEEE 754 floating point library in system-verilog and vhdl

Spinalcrypto ⭐ 36

SpinalHDL - Cryptography libraries

Flickerfixer ⭐ 35

An open source flicker fixer for Amiga 500/2000

Wishbone controlled I2C controllers

A small SoC with a pipeline 32-bit RISC-V CPU.

Neorv32 Verilog ⭐ 35

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Grassrootsstartup Computervsion Zynq ⭐ 35

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

Minimig De1 ⭐ 35

Minimig for the DE1 board

Brianhg Ddr3 Controller ⭐ 34

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Panologic ⭐ 34

PanoLogic Zero Client G1 reverse engineering info

Systemverilogsha256 ⭐ 34

SHA256 in (System-) Verilog / Open Source FPGA Miner

Risc V Cpu ⭐ 34

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

Mangomips32 ⭐ 34

A softcore microprocessor of MIPS32 architecture.

phoeniX RISC-V Processor

Structural Netlist API (and more) for EDA post synthesis flow development

hardware library for hwt (= ipcore repo)

Extensible FPGA control platform

Higan Verilog ⭐ 33

This is a higan/Verilator co-simulation example/framework

Screen Pong ⭐ 33

Pong game in a free FPGA.

Vga Clock ⭐ 33

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Gateware Ts ⭐ 33

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Monocle Fpga ⭐ 32

The FPGA application for Monocle's graphics, camera and microphone accelerators

Cnn_hardware_acclerator_for_fpga ⭐ 32

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Zx Sizif Xxs ⭐ 32

Smallest ZX Spectrum clone with real Z80 and FPGA

Fpga_ntp_server ⭐ 32

A FPGA implementation of the NTP and NTS protocols

Beaglewire ⭐ 32

This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017

Basic Ecp5 Pcb ⭐ 32

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

IBM PC Compatible SoC for a commercially available FPGA board

Fpga Sdft ⭐ 32

sliding DFT for FPGA, targetting Lattice ICE40 1k

Ddr3 Controller ⭐ 32

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

Azure Sdr ⭐ 31

Fp23fftk ⭐ 31

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Speech256 ⭐ 31

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Platform Lattice_ice40 ⭐ 31

Lattice iCE40: development platform for PlatformIO

Core_jpeg ⭐ 31

High throughput JPEG decoder in Verilog for FPGA

Collection of projects for various FPGA development boards

Huaweicloud Fpga ⭐ 30

The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.

Bar Tender ⭐ 30

An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver

Max1000 Tutorial ⭐ 30

Tutorial and example projects for the Arrow MAX1000 FPGA board

Riscv_cpu ⭐ 30

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Caribou: Distributed Smart Storage built with FPGAs

Cλash/Haskell FPGA-based SKI calculus evaluator

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Boxlambda ⭐ 30

FPGA based microcomputer sandbox for software and RTL experimentation

Quokkaevaluation ⭐ 30

Example projects for Quokka FPGA toolkit

FPGA-based AI for Super Mario Bros. Designed for an Altera DE2

Cross EDA Abstraction and Automation

Hyperbus ⭐ 29

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs

Limesdr Pcie_gw ⭐ 29

Altera Cyclone IV FPGA project for the PCIe LimeSDR board

E Verest ⭐ 29

EVEREST: e-Versatile Research Stick for peoples

Evoapproxlib ⭐ 28

Library of approximate arithmetic circuits

Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility

Related Searches

Fpga Vhdl (845)

Fpga Xilinx (551)

C Plus Plus Fpga (359)

Python Fpga (350)

Cpu Verilog (330)

Python Verilog (267)

Verilog Xilinx (265)

Verilog Vhdl (249)

201-300 of 776 search results

Privacy | About | Terms | Follow Us On Twitter

Copyright 2018-2024 Awesome Open Source. All rights reserved.