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13 search results found

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

Vscode Verilog Hdl Support ⭐ 266

HDL support for VS Code

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Virtio implementation in SystemVerilog

Verilator_ext_tests ⭐ 12

Extended and external tests for Verilator testing

Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Ics 2021spring Fdu ⭐ 11

Introduction to Computer Systems (II), Spring 2021.

Croyde Riscv ⭐ 10

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Linter Veriloghdl ⭐ 6

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

SystemVerilog implemention of QEMU PCI edu device

Vga_interface ⭐ 6

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

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