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Search results for fpga hardware acceleration
fpga
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hardware-acceleration
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23 search results found
Brevitas
⭐
1,015
Brevitas: neural network quantization in PyTorch
Qkeras
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514
QKeras: a quantization deep learning library for Tensorflow Keras
Tinytpu
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111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Robotic_processing_unit
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95
A robot-specific processing unit. Contains CPUs, FPGAs and GPUs and maps ROS efficiently to them for best performance.
Tapasco
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87
The Task Parallel System Composer (TaPaSCo)
Community
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51
ROS 2 Hardware Acceleration Working Group community governance model & list of projects
Bnn Icestick
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47
Binary Neural Network on IceStick FPGA.
Krs
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41
The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.
Acceleration_examples
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34
ROS 2 package examples demonstrating the use of hardware acceleration.
Reconros
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16
Easy to use framework for ROS2 FPGA-based hardware acceleration; Supports Pub/Sub communication, Actions and Services and costum ROS Messages
Vivado Hls Broadcast Optimization
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16
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
Pynq 2.7 Mnist
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12
PYNQ-Based MNIST with Tensorflow Lite
Yadan Docs
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11
RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。
Stm32_neuralnet_movementdetection
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10
Motion recognition with artificial intelligence on STM32
Acceleration_firmware_kv260
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9
KV260 firmware. Package for enabling hardware acceleration capabilities in ROS 2 with KV260.
Hls_for_cnn
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7
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Acceleration_firmware_kr260
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7
KR260 Ubuntu 22.04 firmware. Package for enabling hardware acceleration capabilities in ROS 2 Humble with KR260 and Ubuntu 22.04.
Gnn Arch
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6
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Hsa On Fpga
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6
integration of FPGAs in HSA compatible systems
Colcon Hardware Acceleration
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5
An extension for colcon-core to include embedded and Hardware Acceleration capabilities
Adaptive_component
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5
A composable container for Adaptive ROS 2 Node computations. Select between FPGA, CPU or GPU at run-time.
Hls Zybo
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5
A collection of HLS IP designs for Zybo-Z2
Rths
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5
Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm
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1-23 of 23 search results
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