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fpga
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28 search results found
Fusesoc
⭐
1,065
Package manager and build abstraction tool for FPGA/ASIC development
Vtr Verilog To Routing
⭐
925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Openfpga
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692
An Open-source FPGA IP Generator
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Rggen
⭐
261
Code generation tool for configuration and status registers
Systemrdl Compiler
⭐
212
SystemRDL 2.0 language compiler front-end
Open Register Design Tool
⭐
169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Kactus2dev
⭐
168
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Ice Chips Verilog
⭐
99
IceChips is a library of all common discrete logic devices in Verilog
Yosys F4pga Plugins
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81
Plugins for Yosys developed as part of the F4PGA project.
Spydrnet
⭐
66
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Peakrdl
⭐
48
Control and status register code generator toolchain
Ripple Fpga
⭐
47
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Peakrdl Uvm
⭐
41
Generate UVM register model from compiled SystemRDL input
Peakrdl Html
⭐
40
Generate address space documentation HTML from compiled SystemRDL input
Naja
⭐
34
Structural Netlist API (and more) for EDA post synthesis flow development
Xeda
⭐
30
Cross EDA Abstraction and Automation
Peakrdl Ipxact
⭐
29
Import and export IP-XACT XML register models
Eda Scripts
⭐
20
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
Eda Collection
⭐
19
Docker Images
⭐
15
CI Docker Images
Simple Riscv
⭐
13
A simple three-stage RISC-V CPU
Study Materials
⭐
12
Hdl Modules
⭐
10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Awesome Eda
⭐
9
Phi
⭐
7
Hardware description language that tries not to suck
Edapack
⭐
6
Provides a packaged collection of open source EDA tools
Yosys Vscode
⭐
5
Syntax Highlighting for Yosys Scripts and RTLIL
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1-28 of 28 search results
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