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Search results for fpga asic design

14 search results found

Cores Veer Eh1 ⭐ 776

QKeras: a quantization deep learning library for Tensorflow Keras

Cores Veer El2 ⭐ 222

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Openasip ⭐ 124

Open Application-Specific Instruction Set processor tools (OpenASIP)

Neotrng ⭐ 113

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Cnn Accelerator Vlsi ⭐ 48

Convolutional accelerator kernel, target ASIC & FPGA

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

RISCV CPU implementation in SystemVerilog

Rtl Coding ⭐ 6

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Torii Hdl ⭐ 5

A modern hardware definition language and toolchain based on Python

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1-14 of 14 search results

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