Awesome Hdl
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Awesome Hdl | 830 | 3 months ago | 1 | |||||||
| Hardware Description Languages | ||||||||||
| Awesome Open Hardware Verification | 353 | 8 months ago | 1 | mit | ||||||
| A List of Free and Open Source Hardware Verification Tools and Frameworks | ||||||||||
| Awesome Dv | 76 | 2 years ago | ||||||||
| Awesome ASIC design verification | ||||||||||
| Asic Design Roadmap | 49 | a year ago | mit | Verilog | ||||||
| The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges. | ||||||||||
| Verilog Systemverilog Guide | 41 | 4 months ago | SystemVerilog | |||||||
| Verilog/SystemVerilog Guide | ||||||||||
| Awesome Hdl | 14 | 8 years ago | 1 | other | ||||||
| A curated list of awesome HDL, libraries, typical implementation and references. | ||||||||||
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