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Vivado Risc V ⭐ 682

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Multizone Sdk ⭐ 74

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Picorv32_xilinx ⭐ 19

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

The ParaNut Processor - Highly Parallel and More Than Just a CPU Core

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

A RISCV processor in system verilog

Learn Rv32i Arty ⭐ 6

A Simple As Possible RISCV-32I on Digilent Arty board

Riscv_sbc ⭐ 5

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

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