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Openfpgaloader ⭐ 948

Universal utility for programming FPGA

Vitis_libraries ⭐ 770

Vitis Libraries

Run Time for AIE and FPGA based platforms

Trisycl ⭐ 424

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

Sdaccel_examples ⭐ 302

SDAccel Examples

Xfopencv ⭐ 249

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Chaidnn ⭐ 230

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

Gemm_hls ⭐ 184

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

Accelerating Cnn With Fpga ⭐ 164

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

Rosetta ⭐ 127

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Hls_tutorial_examples ⭐ 107

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

Vitis_with_100gbps_tcp Ip ⭐ 103

100 Gbps TCP/IP stack for Vitis shells

Autobridge ⭐ 94

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Thundergp ⭐ 90

HLS-based Graph Processing Framework on FPGAs

Autobridge ⭐ 81

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Sdsoc_examples ⭐ 78

Xc3sprog ⭐ 69

xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs, and EEPROMs with the Xilinx Parallel Cable and other JTAG adapters under Linux. Used to program the FPGA of the MATRIX Creator/Voice via Raspberry Pi.

Ripple Fpga ⭐ 47

RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA

Python/C/RTL cosimulation with Xilinx's xsim simulator

Xup_compute_acceleration ⭐ 41

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

Resnet50 Pynq ⭐ 37

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

Tflite_zynq ⭐ 37

Example code and instructions on getting Tensorflow Lite running on a Xilinx Zynq

bootgen source code

Scalable, Portable and Distributed Gradient Boosting

FPGA acceleration of arbitrary precision floating point computations.

Opencl_xilinx Intel_heterocl ⭐ 19

This is a repo which contains some details about how to use OpenCL backend (Xilinx/Intel).

XRM (Xilinx FPGA Resource Manager) Document:

Hpcc_fpga ⭐ 17

A OpenCL-based FPGA benchmark suite for HPC

IP prototyping in FPGA hardware

Object_detection_on_zynq_mpsoc ⭐ 16

The ParaNut Processor - Highly Parallel and More Than Just a CPU Core

Xvc Esp32 ⭐ 15

Xilinx Virtual Cable implementation for ESP32

Fpga Booleanring Bfs ⭐ 14

Hybrid BFS on Xilinx Zynq

Hls Lenet ⭐ 13

The CNN based on the Xilinx Vivado HLS

Networking Template Library for Vivado HLS

Embeddedcnn ⭐ 13

Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.

Aws F1 Developer Labs ⭐ 12

AWS F1 Xilinx Developer Labs

Bitfile Interpretation Library for Xilinx Virtex FPGAs

Zrobot_v1 ⭐ 11

The robot base on ZedBoard

Tinyyolo Bnn ⭐ 11

Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.

Logisticregression ⭐ 11

Logistic regression FPGA core

Fireprog ⭐ 10

A tool for configuring Xilinx Spartan 3 FPGAs via FT232H-based USB-to-JTAG adapter

A C++ template library for FPGAs on top of Xilinx Vivado HLS

Ultra96 Fractal ⭐ 9

Hardware accelerated Julia set explorer running on Ultra96

DaCH: dataflow cache for high-level synthesis.

Hls_ldpc_dec ⭐ 9

Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..

Simpletpu ⭐ 9

A CNN accelerator, following Google's TPU V1.

Aws Fpga Simple Example ⭐ 9

A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.

Pymtl Tut Hls ⭐ 8

Tutorial for integrating PyMTL and Vivado HLS

Video_power_workshop ⭐ 7

A toolset of controling system based on Xilinx Zybo board and OpenCV

Xilinx_readback_verify ⭐ 7

A simple tool for verifying readback data for Xilinx Virtex 5 and 7-series devices

Miscellaneous things and projects for my ZYBO and ZYNQ devices.

Core_sdram_axi4 ⭐ 7

SDRAM controller with AXI4 interface

Binomialmodel ⭐ 6

A RISCV processor in system verilog

Faiss Fpga ⭐ 6

An FPGA integration and acceleration of the popular FAISS framework for approximate similarity search

Get_moving_with_alveo ⭐ 6

For publishing the source for UG1352 "Get Moving with Alveo"

Zybo Linux ⭐ 6

A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here.

Clone of the SF SVN tree, adding embedded 'cable' support

Sme Developer Labs ⭐ 6

P4 compatible HLS modules

Irn Vivado Hls ⭐ 5

IRN's packet processing logic synthesized using Xilinx Vivado HLS

Xilinx_code_templates ⭐ 5

Collection of simple examples and drivers for peripherals for Xilinx processors (Microblaze and ARM Cortex A9 in Zynq). Languages used: C and C++.

Spartan3 programming tools for GNU/Linux

BWA SW (ksw_extend2) in VivadoHLS and SDAccel

Zynq7 Sdr ⭐ 5

Software defined radio receiver on the Zynq7 SoC

Sdaccel_perf_benchmark ⭐ 5

SDAccel project intended to predict, build for, and measure performance of Xilinx FPGAs.

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