Zynq7 Sdr
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Rfnoc Hls Neuralnet | 61 | 5 years ago | 4 | gpl-3.0 | CMake | |||||
| Amalthea | 32 | a year ago | 1 | bsd-3-clause | Python | |||||
| an experimental SDR platform | ||||||||||
| Sweepsense | 23 | 5 months ago | 2 | apache-2.0 | Python | |||||
| FPGA code and Python API for adding chirp functionality to USRP N210 with CBX daughter board, after the required hardware modification. | ||||||||||
| Theseus Cores | 8 | 3 years ago | 1 | Verilog | ||||||
| Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores) | ||||||||||
| Zynqgnuradio | 6 | 7 years ago | C | |||||||
| FPGA accelerator on GNU Radio and Zynq SoC | ||||||||||
| Zynq7 Sdr | 5 | 8 years ago | gpl-2.0 | C++ | ||||||
| Software defined radio receiver on the Zynq7 SoC | ||||||||||
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