Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for verilog circuit
circuit
x
verilog
x
52 search results found
Logisim Evolution
⭐
4,251
Digital logic design tool and simulator
Digital
⭐
3,476
A digital logic designer and circuit simulator.
Circt
⭐
1,431
Circuit IR Compilers and Tools
Cello
⭐
616
Genetic circuit design automation
Minecrafthdl
⭐
595
A Verilog synthesis flow for Minecraft redstone circuits
Ucr Eecs168 Lab
⭐
423
The lab schedules for EECS168 at UC Riverside
Magma
⭐
234
magma circuits
Scale Mamba
⭐
189
Repository for the SCALE-MAMBA MPC system
Breaks
⭐
138
Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing
Icemu
⭐
113
Emulate Integrated Circuits at the logic level
Tinygarble
⭐
113
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Benchmarks
⭐
102
EPFL logic synthesis benchmarks
Ice Chips Verilog
⭐
99
IceChips is a library of all common discrete logic devices in Verilog
Circuitgraph
⭐
74
Tools for working with circuits as graphs in python
Spydrnet
⭐
66
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
D3 Hwschematic
⭐
64
D3.js and ELK based schematic visualizer
Vossii
⭐
47
The source code to the Voss II Hardware Verification Suite
Yosys2digitaljs
⭐
41
Export netlists from Yosys to DigitalJS
Mantle
⭐
38
mantle library
Pychip Py Hcl
⭐
35
A Hardware Construct Language
Haski
⭐
30
Cλash/Haskell FPGA-based SKI calculus evaluator
Icarus_verilog
⭐
28
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
Evoapproxlib
⭐
28
Library of approximate arithmetic circuits
Parser Verilog
⭐
24
A Standalone Structural Verilog Parser
Reqack
⭐
23
🔁 elastic circuit toolchain
Blasys
⭐
21
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Async Karin
⭐
17
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
Verilog Starter Tutorials
⭐
17
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
Flicker Noise
⭐
15
How to correctly write a flicker-noise model for RF simulation.
Idea
⭐
14
Ce202 Lc Lab Manual
⭐
14
Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
Getting Started With Verilog
⭐
12
Verilog modules for beginners
Digital Design
⭐
11
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
Pershing
⭐
11
An automatic place-and-route tool for Minecraft redstone circuits
Fpga_spi
⭐
11
Connecting FPGA and Arduino using SPI.
Coco Alma
⭐
10
Awesome Eda
⭐
9
Usb Blaster_uart
⭐
9
UART via USB-Blaster with VirtualJTAG.
Glitchhammer
⭐
8
A custom coprocessor and SoC for hardware security experiments in electronics.
Mpcircuits
⭐
8
Optimized Circuit Generation for Secure Multiparty Computation
Loam
⭐
8
Loam system models
Mchyper
⭐
7
A hardware model checker for hyperproperties
Uw Idea_analogtestcases
⭐
7
Circuit Release for Analog Test Cases from UW IDEA project
Dft
⭐
7
Ttu Lab1 Code Examples
⭐
7
Example code for Project Lab 1
Chip Design
⭐
7
Design and Verification of a Complete Application Specific Integrated Circuit
Dewey
⭐
6
C version of PERSHING, a place-and-route tool for Minecraft Redstone circuits
Verilog Parser
⭐
6
A verilog parser
Verilog
⭐
6
learning VHDL
Libcircuit
⭐
6
libCircuit is a C++ Library for EDA software development
Incremental Sat Decam
⭐
5
Project website of Incremental-SAT based De-camouflaging of logic circuits
Pulsar
⭐
5
Pulsar asynchronous synthesis framework
Digiblock
⭐
5
Ruby_rtl
⭐
5
Describing RTL circuit in Ruby
Related Searches
Verilog Fpga (1,343)
Python Circuit (625)
C Plus Plus Circuit (557)
Javascript Circuit (348)
Circuit Quantum (332)
Cpu Verilog (330)
Java Circuit (292)
C Circuit (278)
Python Verilog (267)
Verilog Xilinx (265)
1-52 of 52 search results
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.