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Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

Risc V Core ⭐ 5

A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.

RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python

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