Awesome Open Source

Programming Languages

Search results for register verilog

35 search results found

Code generation tool for configuration and status registers

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Haskell library for hardware description

A very primitive but hopefully self-educational CPU in Verilog

Control and status register code generator toolchain

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

Pyverilog_toolbox ⭐ 17

Multi-cycle pipelined ARM-LEGv8 CPU with Forwarding and Hazard Detection.

Ics Adpcm ⭐ 16

Programmable multichannel ADPCM decoder for FPGA

Midi Stepper Synth V2 ⭐ 15

Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors.

Mostly AVR compatible FPGA soft-core

Open_regmodel ⭐ 13

🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

Riscv Core ⭐ 11

A customized RISCV core made using verilog

Fpganes_release ⭐ 11

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

Riscv_soc ⭐ 10

Basic RISC-V Test SoC

Pipelined Mips ⭐ 10

A Verilog implementation of a pipelined MIPS processor

A Tcl-Library for scripted HDL generation

Ultimem64 ⭐ 9

Commodore 64 Internal RAM Expansion with integrated MMU

Pulse Width Modulation Ip ⭐ 8

A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)

4 BIT Original CPU

Simple_reg_model ⭐ 8

System verilog register model for uvm testbenches.

8bit Computer ⭐ 8

Simple 8-bit computer build in Verilog

Tang Nano_midi_sounder ⭐ 7

Ece241_verilog ⭐ 7

This repo contains all the Verilog HDL files that I made during the course.

Cic_prune ⭐ 6

A C version of Rick Lyon's Matlab implementation of Hogenauer's CIC filter register pruning algorithm

Sap 1 V2 Mojo ⭐ 5

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

Minicpu S ⭐ 5

Minimal Stack-based CPU for CPLDs with Serial ALU and SPI-based Memory/IO

Tang Nano_partyparrot ⭐ 5

A CPU that implementing THCO-MIPS16 instruction set.

Minimal RISC-V Implementation

Core_audio ⭐ 5

Audio controller (I2S, SPDIF, DAC)

Related Searches

Javascript Register (1,475)

Verilog Fpga (1,343)

Php Register (1,060)

Python Register (890)

Java Register (609)

Login Register (581)

C Register (468)

C Plus Plus Register (401)

Cpu Verilog (330)

Python Verilog (267)

1-35 of 35 search results

Privacy | About | Terms | Follow Us On Twitter

Copyright 2018-2024 Awesome Open Source. All rights reserved.