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Search results for python verilog
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verilog
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159 search results found
Mobile Fpga Bluetooth Demo
⭐
10
Simple BLE demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)
Verilog Template
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10
Regal
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10
A set of scripts used to assist reverse engineering of old-school Programmable Array Logic devices.
Pythondata Cpu Rocket
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10
Python module containing verilog files for rocket cpu (for use with LiteX).
Coco Alma
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10
Pyedaa.projectmodel
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10
An abstract model of EDA tool projects.
Crunchy
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9
Distributed FPGA Number Crunching for the Masses
Teroshdl Documenter Demo
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9
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
Spi2wb
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9
Drive a Wishbone master bus with an SPI bus.
Sydpy
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9
System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to SystemVerilog and other HDLs.
Hdlgen Chatgpt
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9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
Glacial
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9
Glacial - microcoded RISC-V core designed for low FPGA resource utilization
Python To Verilog
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9
Generate a Verilog Source file and testbench file for a given Moore FSM
Nexus
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9
Open source RTL simulation acceleration on commodity hardware
Verilogparser
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8
Simple Verilog Parser In Python
Project2064
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8
XC2064 bitstream documentation
Dds
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8
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
Manta
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8
An In-Situ Debugging Tool for Programmable Hardware
F4pga V2x
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8
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
Complex_multiplier
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8
HDL code for a complex multiplier with AXI stream Interface
Verilog_vcd
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8
https://pypi.python.org/pypi/Verilog_VCD
Mycpu
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8
Simple cpu in Verilog + Assembler in c and python
Synthia
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8
an IDE that uses myHDL, yosys, and arachne-pnr to target the ICEStick
Verilog_integration
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8
example of python vpi integration
Pysvinst
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8
Python library for parsing module definitions and instantiations from SystemVerilog files
Rc4 Verilog
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8
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Tsinghua Ee Miscellanea
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8
🐾 Miscellanious projects during 2014-2018 in Dept. of Electronic Engineering, Tsinghua University
Verilog Ft245
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8
Verilog FT245 to AXI stream interface
Makeise
⭐
7
Simple script to automatically generate ISE project files
Vscode_extension_verilog
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7
VSCode extension for enhancing verilog
Gtuedu
⭐
7
Gebze Technical University
Sphinx Hwt
⭐
7
Sphinx extension for visual documentation of hardware written in HWT
Py4hw
⭐
7
Hardware Design/Visualization/Simulation/RTLGeneration Framework
Mitecpu
⭐
7
Minimal microprocessor
Digsim
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7
An interactive digital logic simulator with verilog support (Yosys)
Systemverilog2verilog
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7
Converting systemverilog to verilog.
Tizzy
⭐
6
Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python
Cic
⭐
6
HDL code for a complex multiplier with AXI stream interface
Edapack
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6
Provides a packaged collection of open source EDA tools
Pyxhdl
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6
Python Frontend For VHDL And Verilog
Svmodule
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6
SystemVerilog & Verilog Module I/O parser and printer
Usb Device
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6
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Animatevcd
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6
animate an SVG with a VCD file
Cse Lab Solutions
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6
Comprehensive CSE Lab Solutions repo; encompassing all my lab manuals, codes, documents, and endsem questions from my B.Tech program (2020-2024).
Verilog2spice
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6
Simple strutured VERILOG netlist to SPICE netlist translator
Ipcorepackager
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6
Scriptable IP-Core generator
Icysprites
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5
The easiest to use sprite-based graphics kit for FPGAs
Fpga Project Eie1
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5
Implementing interactive music controls on FPGAs done as a coursework for EIE1 First Year Project
Microcoder
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5
Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.
Legohdl
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5
An experimental package manager and development tool for Hardware Description Languages (HDL).
Drfm
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5
Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"
Sublimelinter Contrib Xsim
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5
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
Fmcw
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5
6GHz frequency-modulated continuous-wave radar with real-time range detection
Cli
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5
Official WebFPGA Command-line Utility
Fft
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5
FFT algorithm for fpga
Cocotbext I2c
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5
I2C models for cocotb
Ft232h_communication
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5
Sphinx Verilog Domain
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5
Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
Vtags
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5
Verdi like, verilog code signal trace and show hierarchy script
Pythondata Cpu Blackparrot
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5
Python module containing system_verilog files for blackparrot cpu (for use with LiteX).
Wavedisp
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5
Python classes to create agnostic wave files for HDL simulator viewer
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101-159 of 159 search results
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