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fpga
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pll
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3 search results found
Dpll
⭐
82
A collection of phase locked loop (PLL) related projects
Eda Scripts
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20
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
Bit_error_tester
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5
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
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