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Search results for fpga accelerator
accelerator
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fpga
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91 search results found
Neural Networks On Silicon
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1,696
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
Pipecnn
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916
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Yolov2_xilinx_fpga
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624
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
Qkeras
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514
QKeras: a quantization deep learning library for Tensorflow Keras
Zynqnet
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510
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
Heterocl
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281
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Esp
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267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Bnn Fpga
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218
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
Fletcher
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217
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
Accelerating Cnn With Fpga
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164
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
Accdnn
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121
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Dcompute
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116
DCompute: Native execution of D on GPUs and other Accelerators
Fpga_based_cnn
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113
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
Sycl
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98
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Transfomers Silicon Research
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97
Research and Materials on Hardware implementation of Transformer Model
Thundergp
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90
HLS-based Graph Processing Framework on FPGAs
Tapasco
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87
The Task Parallel System Composer (TaPaSCo)
Rapid Design Methods For Developing Hardware Accelerators
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84
Caffepresso
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80
CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms
Skrskr
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76
The second place winner for DAC-SDC 2020
Tf2
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74
An Open Source Deep Learning Inference Engine Based on FPGA
Pynq Project
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65
PYNQ, Neural network Language model, Overlay
Fpga Zynqnet
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56
FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
Basic_knowledge
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53
Things to learn for new students in the Lab for AI chips and systems of BJTU .
Cnn Accelerator Vlsi
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48
Convolutional accelerator kernel, target ASIC & FPGA
Bigpulp
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48
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
Marlann
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46
Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
Dnn Accelerator
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45
A DNN Accelerator implemented with RTL.
Sneakysnake
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44
SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs/1910.09020.
Fos
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40
FOS - FPGA Operating System
Deep Neural Network Hardware Accelerator
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40
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
Accelerator Docker
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35
Accelerator-Docker : provides common interface for automatic passthrough of heterogeneous hardware accelerators in docker
Neural Networks On Silicon
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32
This is a collection of works on neural networks and neural accelerators.
Deepburning
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32
Automatic generation of FPGA-based learning accelerators for the neural network family
Autooffload.jl
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29
Automatic GPU, TPU, FPGA, Xeon Phi, Multithreaded, Distributed, etc. offloading for scientific machine learning (SciML) and differential equations
E Verest
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29
EVEREST: e-Versatile Research Stick for peoples
Numerical Fpga Thesis
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28
Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH
Awslabs
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23
Accel Docker
⭐
22
Rosetta
⭐
21
Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
Xgboost
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20
Scalable, Portable and Distributed Gradient Boosting
Hls Cnn
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19
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
Fpga Dcnn Accelerator
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19
基于HLS的高效深度卷积神经网络FPGA实现方法
Cnn_vhdl_generator
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18
AUTOMATIC VHDL GENERATION FOR CNN MODELS
Free Tpu V3plus For Fpga
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18
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
Open Dnn
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18
Pipecnn_winograd
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17
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
Spartan Edge Accelerator Graphical System
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16
WIP Graphics layer and inter IC communication for the Spartan Edge Accelerator fpga/mcu hybrid board
Nvdla Wrapper
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16
Wraps the NVDLA project for Chipyard integration
Cho
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15
CHO is a benchmark suite for OpenCL FPGA Accelerators
Hog_zedboard
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14
A real time Histogram of Oriented Gradients Implementation on FPGA
Vp_awsfpga
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13
Virtual Platform for AWS FPGA support
Study Materials
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12
Aws F1 Developer Labs
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12
AWS F1 Xilinx Developer Labs
Iota_fpga
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12
FPGA based hardware accelerator for IOTA Curl and POW operations
Dyract
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12
DyRACT Open Source Repository
Ck Tvm
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12
Portable and customizable Collective Knowledge workflows for TVM and VTA:
Cnn_hw_accelerator
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12
FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
Aws Fpga Firesim
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11
AWS Shell for FireSim
Finance.zynqpricer.hls
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11
Heston implementation for Zynq with Vivado HLS
Logisticregression
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11
Logistic regression FPGA core
Deep Learning Hardware Accelerator
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11
Paper Collection of Deep Learning Hardware Accelerator
Opencapi3.0_client_refdesign
⭐
10
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
M Blanc
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10
MBLANC: mini Board Lab and Companion
Opae Xilinx
⭐
10
OPAE porting to Xilinx FPGA devices.
Memluv
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9
An HLS-synthesizable Dynamic Memory Manager for FPGAs
Fusionaccel
⭐
9
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
Genwqe User
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9
The project uses a PCIe-Card for FPGA based zlib acceleration. This project provides a hardware accelerated version of zLib based compression/decompression RFC1950/RFC1951/RFC1952 with help of an FPGA based PCIe card.
Scalabfs
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9
A Scalable BFS Accelerator on FPGA-HBM Platform
Fpga Video Decoder
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8
👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.
Lin Analyzer
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8
A high-level performance analysis tool for FPGA-based accelerators
Opencl_fpga
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8
C# ETH Miner - FPGA (520S Stratix10/385A Arria10)
Shouji
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8
Shouji is fast and accurate pre-alignment filter for banded sequence alignment calculation. Described in the Bioinformatics journal paper (2019) by Alser et al. at https://academic.oup.com/bioinformatics/advance-ar
Vgg16_fpga_accelerator
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8
A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).
Posit_blas_hdl
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7
Posit Arithmetic Accelerator interfacing with Apache Arrow & CAPI SNAP
Hls_for_cnn
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7
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Hls_blstm
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7
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
Riffa
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7
RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This project utilises the RIFFA framework to define an interface to interact with a user's IP core on the FPGA to send and receive data to and from the PC. This particular project is being developed under Imperial College London.
Sha256_hw_accelerator
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7
SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent
Dhl
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6
An FPGA-CPU co-design framework for accelerating software NFs (Network Functions) with Intel DPDK
Accelerator K8s
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6
Kubernetes device plugin supporting FPGA and other accelerators
Sme Developer Labs
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6
Improving_per_esti_for_fpga Based_acc_for_cnns Arc2020
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6
A codebase accompanying the paper "Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks", by Ferianc et al. presented at ARC'2020
Oswald
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6
OpenCL Smith-Waterman Algorithm on Altera FPGA for Large Protein Databases
Gnn Arch
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6
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Awesome Fpga Boards
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5
Second life for FPGA boards which can be repurposed
Deep Learning Resources
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5
Getting Started with Deep learning resources
Heterogeneous Papers
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5
A reading list of some interesting papers about heterogeneous systems.
Cannon Fpga
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5
S2fa
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5
An automated Spark to FPGA accelerator framework.
Centrifuge
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5
Apyfal
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5
Visual System Integrator
⭐
5
Visual System Integrator - Accelerate your embedded development
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