Computer Organization And Architecture Lab
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vexriscv | 2,135 | 4 months ago | 100 | mit | Assembly | |||||
| A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| E200_opensource | 1,688 | 3 years ago | 33 | apache-2.0 | Verilog | |||||
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 | ||||||||||
| Neorv32 | 1,337 | 3 months ago | 15 | bsd-3-clause | VHDL | |||||
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
| Zipcpu | 1,139 | 3 months ago | 4 | Verilog | ||||||
| A small, light weight, RISC CPU soft core | ||||||||||
| E203_hbirdv2 | 741 | a year ago | 10 | apache-2.0 | Verilog | |||||
| The Ultra-Low Power RISC-V Core | ||||||||||
| Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
| Kianriscv | 396 | 4 months ago | isc | AGS Script | ||||||
| KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, . | ||||||||||
| Risc V Single Cycle Cpu | 380 | a year ago | mit | Verilog | ||||||
| A RISC-V 32bit single-cycle CPU written in Logisim | ||||||||||
| Riscv | 364 | 3 years ago | 4 | bsd-3-clause | Verilog | |||||
| RISC-V CPU Core (RV32IM) | ||||||||||
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