| apertus-open-source-cinema/axiom-firmware |
160 |
|
0 |
0 |
over 2 years ago |
0 |
|
62 |
gpl-3.0 |
VHDL |
| AXIOM firmware (linux image, gateware and software tools) |
| daveshah1/openMixR |
24 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
mit |
VHDL |
| 4k Mixed Reality headset |
| Rutgers-FPGA-Projects/Camera-Tracking |
18 |
|
0 |
0 |
over 12 years ago |
0 |
|
0 |
|
VHDL |
| Our project is the system that enables a moving camera to track a moving object in real time. We plan on doing this by having a camera mounted to a swivel using two servo motors to allow for the camera’s direction to be controlled. The camera data will be read into the FPGA board and some basic object recognition algorithm will be used to identify an some object and determine if the camera needs to be moved to keep the object in the field of vision. In addition to the auto tracking mode, we plan on having an IR remote to allow for manual panning, mode selection, and power on and off. If there is additional time we would like to also interface the FPGA to a Raspberry Pi board running a linux web server to allow for email alerts (when object moves) and web based control. |
| lllbbbyyy/FPGA-OV2640 |
17 |
|
0 |
0 |
over 5 years ago |
0 |
|
2 |
mit |
VHDL |
| This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA. |
| andrewandrepowell/zybo_petalinux_video_hls |
16 |
|
0 |
0 |
almost 10 years ago |
0 |
|
0 |
|
VHDL |
| Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output. |
| bitflippersanonymous/fpga-camera |
10 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| FPGA digital camera controller and frame capture device in VHDL |
| Archfx/FPGA-DepthMap-Basys3 |
8 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
VHDL |
| Real Time depth map generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions. |
| alessandro-montanari/vhdl-project |
6 |
|
0 |
0 |
about 11 years ago |
0 |
|
0 |
|
VHDL |
| Implementation in VHDL of the Sobel edge detection operator |
