| platformio/platformio-atom-ide |
474 |
|
0 |
0 |
over 5 years ago |
0 |
|
20 |
apache-2.0 |
JavaScript |
| PlatformIO IDE for Atom: The next generation integrated development environment for IoT |
| EttusResearch/fpga |
192 |
|
0 |
0 |
over 4 years ago |
0 |
|
0 |
|
Verilog |
| The USRP™ Hardware Driver FPGA Repository |
| benreynwar/pyvivado |
60 |
|
0 |
0 |
about 7 years ago |
0 |
|
1 |
mit |
Python |
| Python tools for Vivado Projects |
| mhamdan91/cnn_vhdl_generator |
18 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
mit |
VHDL |
| AUTOMATIC VHDL GENERATION FOR CNN MODELS |
| RAPcores/rapcores |
13 |
|
0 |
0 |
over 4 years ago |
0 |
|
28 |
isc |
Verilog |
| Robotic Application Processor |
| RTC-research-group/OpenNAS |
12 |
|
0 |
0 |
over 4 years ago |
0 |
|
4 |
gpl-3.0 |
C# |
| OpenN@S: Open-source software to NAS automatic VHDL code generation |
| kazuyamashi/cReComp |
10 |
|
0 |
0 |
almost 8 years ago |
16 |
February 17, 2017 |
0 |
bsd-3-clause |
Python |
| Archfx/FPGA-DepthMap-Basys3 |
8 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
VHDL |
| Real Time depth map generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions. |
