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Search results for write verilog

11 search results found

Iob Cache ⭐ 134

Verilog Configurable Cache

Sdram_controller ⭐ 16

Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)

Hardcaml_of_verilog ⭐ 15

Convert Verilog to a Hardcaml design

4 Way Set Associative Cache Verilog ⭐ 14

Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

Zc Riscv Core ⭐ 11

Coding_practice ⭐ 11

This is the code I write for school, and some little code which is fun. Just recording what I learned.

Drive a Wishbone master bus with an SPI bus.

Sata3_host_controller ⭐ 9

It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.

Hardcaml Yosys ⭐ 8

[DEPRECATED] Import verilog designs into hardcaml using yosys

Asynchronous Fifo ⭐ 7

Asynchronous fifo in verilog

Rnbip_singlebusprocessor ⭐ 7

Single Bus Processor - Summer Project 2016

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