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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

RISCV CPU implementation in SystemVerilog

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Risc V Core ⭐ 5

A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.

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