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Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Code generation tool for configuration and status registers

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.

Azadi Soc ⭐ 16

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

Sha256hasher ⭐ 15

SHA-256 IP core for ZedBoard (Zynq SoC)

Open SoC Debug Hardware Reference Implementation

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Axi_spi_slave ⭐ 8

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