Awesome Open Source

Programming Languages

Search results for rtl soft core

1 search results found

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Fpga Ddr Sdram ⭐ 83

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Tree Core Cpu ⭐ 29

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Udarkrisc ⭐ 9

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Related Searches

Rtl Software Defined Radio (392)

Javascript Rtl (288)

Verilog Rtl (227)

Rtl Systemverilog (71)

Rtl Risc V (41)

Fpga Soft Core (18)

Rtl Verilator (14)

1-1 of 1 search results

Privacy | About | Terms | Follow Us On Twitter

Copyright 2018-2024 Awesome Open Source. All rights reserved.