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Search results for scala rtl

29 search results found

Chisel ⭐ 3,685

Chisel: A Modern Hardware Design Language

Rocket Chip ⭐ 2,988

Rocket Chip Generator

Riscv Boom ⭐ 1,524

SonicBOOM: The Berkeley Out-of-Order Machine

Spinalhdl ⭐ 1,451

Scala based HDL

Firesim ⭐ 778

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Riscv Mini ⭐ 427

Simple RISC-V 3-stage Pipeline in Chisel

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Saxonsoc ⭐ 133

SoC based on VexRiscv and ICE40 UP5K

Constellation ⭐ 125

A Chisel RTL generator for network-on-chip interconnects

Spinalworkshop ⭐ 117

Labs to learn SpinalHDL

high-performance RTL simulator

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Riscv Torture ⭐ 68

RISC-V Torture Test

Spinalcrypto ⭐ 36

SpinalHDL - Cryptography libraries

Tree Core Cpu ⭐ 29

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Hardposit Chisel3 ⭐ 26

Chisel library for Unum Type-III Posit Arithmetic

Boom Template ⭐ 23

A template for building new projects/platforms using the BOOM core.

Spatten Llm ⭐ 22

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

Chisel Things for OFDM

Quasar 2.0: Chisel equivalent of SweRV-EL2

Neuralhdl ⭐ 13

Spinaldev ⭐ 12

Docker Development Environment for SpinalHDL

Midas Examples ⭐ 8

Simple MIDAS Examples

Rocket Chip Rocc ⭐ 8

This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.

Midas Top Release ⭐ 7

MIDAS RocketChip Template

Midas Release ⭐ 6

MIDAS Public Release

BOOM's Simulation Accelerator.

Introductory Guide To Chisel ⭐ 5

「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ

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