Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Cores	302	3 years ago	3		Verilog
Various HDL (Verilog) IP Cores
Midas	81	4 years ago	8	bsd-3-clause	Scala
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
Zbc The Zero Board Computer	15	4 years ago	1	gpl-3.0	Verilog
Based heavily on zet.aluzina.org and Terasic DE0
Jtag_dpi	13	8 years ago	2		SystemVerilog
JTAG DPI module for SystemVerilog RTL simulations

Alternatives To Midas

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Cores ⭐ 302

Various HDL (Verilog) IP Cores

most recent commit 3 years ago

Midas ⭐ 81

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

most recent commit 4 years ago

Zbc The Zero Board Computer ⭐ 15

Based heavily on zet.aluzina.org and Terasic DE0

most recent commit 4 years ago

Jtag_dpi ⭐ 13

JTAG DPI module for SystemVerilog RTL simulations

most recent commit 8 years ago

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Alternative Project Comparisons

Midas vs Cores

Midas vs Zbc The Zero Board Computer

Midas vs Jtag_dpi

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