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19 search results found

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Concurrency ⭐ 537

Java 并发编程知识梳理以及常见处理模式 features and patterns

Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Realtek Mips Sdks ⭐ 50

Realtek Network SoC/CPU toolchains (including support for Lexra based chips)

Simplecpu ⭐ 30

An open source CPU design and verification platform for academia

Tree Core Cpu ⭐ 29

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Spinaldev ⭐ 12

Docker Development Environment for SpinalHDL

Udarkrisc ⭐ 9

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Pequeno_riscv ⭐ 8

Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I

Custom 64-bit pipelined RISC processor

a simple 2 stage cpu in verilog

Small microcoded 68000 verilog softcore

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