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Search results for rtl soc

23 search results found

Chipyard ⭐ 1,393

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Code generation tool for configuration and status registers

Libsystemctlm Soc ⭐ 175

SystemC/TLM-2.0 Co-simulation framework

Saxonsoc ⭐ 133

SoC based on VexRiscv and ICE40 UP5K

Constellation ⭐ 125

A Chisel RTL generator for network-on-chip interconnects

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Realtek Mips Sdks ⭐ 50

Realtek Network SoC/CPU toolchains (including support for Lexra based chips)

hardware library for hwt (= ipcore repo)

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

Rtl8710_vga_display_driver ⭐ 12

VGA Driver for RTL8710, RTL8711 and RTL8195 SoC

Cgraflowdoc ⭐ 11

Documentation for the entire CGRAFlow

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Zet - The x86 (IA-32) open implementation

Barebonescortexm0 ⭐ 7

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

Openxc7 Tetrisaraj ⭐ 7

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

BOOM's Simulation Accelerator.

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1-23 of 23 search results

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