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Search results for risc v

753 search results found

Ncnn ⭐ 19,097

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Rt Thread ⭐ 9,221

RT-Thread is an open source IoT real-time operating system (RTOS).

Platformio Core ⭐ 7,474

Your Gateway to Embedded Software Development Excellence 👽

Capstone ⭐ 7,055

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

Unicorn ⭐ 6,921

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Xv6 Riscv ⭐ 5,550

A secure embedded operating system for microcontrollers

Tengine ⭐ 4,452

Tengine is a lite, high performance, modular inference engine for embedded device

Alios Things ⭐ 4,437

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun

Dietpi ⭐ 4,339

Lightweight justice for your single-board computer!

Xiangshan ⭐ 4,180

Open-source high-performance RISC-V processor

Os_kernel_lab ⭐ 3,895

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

Rcore ⭐ 3,099

Rust version of THU uCore OS. Linux compatible.

Rocket Chip ⭐ 2,988

Rocket Chip Generator

Ripes ⭐ 2,266

A graphical processor simulator and assembly editor for the RISC-V ISA

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Reko is a binary decompiler.

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Awesome Cpus ⭐ 1,735

All CPU and MCU documentation in one place

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Riscv Boom ⭐ 1,524

SonicBOOM: The Berkeley Out-of-Order Machine

Chipyard ⭐ 1,393

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Renode ⭐ 1,332

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Rcore Tutorial V3 ⭐ 1,327

Let's write an OS which can run on RISC-V in Rust from scratch!

Probe Rs ⭐ 1,325

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

The official repository for the gem5 computer-system architecture simulator.

Risc0 ⭐ 1,231

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SERV - The SErial RISC-V CPU

RARS -- RISC-V Assembler and Runtime Simulator

Rcore Tutorial Book V3 ⭐ 1,062

A book about how to write OS kernels in Rust easily.

A self-hosting and educational C optimizing compiler

Rustsbi ⭐ 873

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/standalone.

Tinyriscv ⭐ 865

A very simple and easy to understand RISC-V core.

Cv32e40p ⭐ 861

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Riscv V Spec ⭐ 801

Working draft of the proposed RISC-V V vector extension

Riscv Cores List ⭐ 791

RISC-V Cores, SoC platforms and SoCs

Firesim ⭐ 778

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Cores Veer Eh1 ⭐ 770

The RISC-V Virtual Machine

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

Unix-like OS in Rust inspired by xv6-riscv

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Vivado Risc V ⭐ 682

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

RISC-V simulator for x86-64

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

RISC-V VMs in Minecraft.

Awesome Embedded Software ⭐ 579

🌠 List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

Eclipse Plugins ⭐ 552

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A 32-bit RISC-V emulator in a shader (and C)

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

Edk2 Platforms ⭐ 486

EDK II sample platform branches and tags

Eunomia Bpf ⭐ 482

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

Riscv Rust ⭐ 444

RISC-V processor emulator written in Rust+WASM

Dirtyjtag ⭐ 431

JTAG probe firmware

Pulp Dronet ⭐ 428

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Riscv Mini ⭐ 427

Simple RISC-V 3-stage Pipeline in Chisel

Riscv Debug Spec ⭐ 419

Working Draft of the RISC-V Debug Specification Standard

Risc V Guide ⭐ 406

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Jupiter ⭐ 403

RISC-V Assembler and Runtime Simulator

Kianriscv ⭐ 396

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

Riscv Openocd ⭐ 395

Fork of OpenOCD that has RISC-V support

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Risc V Single Cycle Cpu ⭐ 380

A RISC-V 32bit single-cycle CPU written in Logisim

Lbforth ⭐ 379

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Libriscv ⭐ 371

C++20 RISC-V RV32/64/128 userspace emulator library

Riscv Card ⭐ 369

An unofficial assembly reference for RISC-V.

RISC-V CPU Core (RV32IM)

Core V Verif ⭐ 359

Functional verification project for the CORE-V family of RISC-V cores.

Riscv Software List ⭐ 353

The RISC-V software tools list, as seen on riscv.org

World Of Warcraft 3.3.5a server

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

Verigpu ⭐ 323

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Meta Riscv ⭐ 323

OpenEmbedded/Yocto layer for RISC-V Architecture

Small & portable byte-aligned LZ77 compression

CKB's vm, based on open source RISC-V ISA

Bouffalo_sdk ⭐ 317

BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk

Udbserver ⭐ 309

Unicorn Emulator Debug Server - Written in Rust, with bindings for C, Go, Java and Python

Projects ⭐ 307

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Awesome Sgx Open Source ⭐ 295

A curated list of open-source projects that help exploit Intel SGX technology

Rv32emu ⭐ 295

Compact and Efficient RISC-V RV32I[MACF] emulator

Mipt Mips ⭐ 291

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

Homebrew Riscv ⭐ 281

homebrew (macOS) packages for RISC-V toolchain

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Tool to generate ROP gadgets for ARM, AARCH64, x86, MIPS, PPC, RISCV, SH4 and SPARC

RISC-V CPU Core

An easy way to virtualize the running system

Bao Hypervisor ⭐ 268

Bao, a Lightweight Static Partitioning Hypervisor

Fpga Zynq ⭐ 268

Support for Rocket Chip on Zynq FPGAs

Riscv Fs ⭐ 268

F# RISC-V Instruction Set formal specification

Ataraxia ⭐ 268

Simple and lightweight source-based multi-platform Linux distribution with musl libc.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Bedrock2 ⭐ 266

A work-in-progress language and compiler for verified low-level programming

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