Riscv V Spec
Working draft of the proposed RISC-V V vector extension
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Riscv V Spec | 801 | 5 months ago | 125 | cc-by-4.0 | Assembly | |||||
| Working draft of the proposed RISC-V V vector extension | ||||||||||
| Ara | 276 | 5 months ago | 57 | other | C | |||||
| The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core | ||||||||||
| Imperas Riscv Tests | 123 | 6 months ago | 12 | C | ||||||
| Simd_utils | 65 | 6 months ago | 2 | bsd-2-clause | C | |||||
| A header only library implementing common mathematical functions using SIMD intrinsics | ||||||||||
| Riscv Vectorized Benchmark Suite | 48 | a year ago | 3 | other | C++ | |||||
| RiVEC Bencmark Suite | ||||||||||
| Dl_accelerator | 44 | 4 years ago | 5 | Scala | ||||||
| Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions | ||||||||||
| Rvv Kernels | 16 | a year ago | Assembly | |||||||
| Implements kernels with RISC-V Vector | ||||||||||
| Llvm Rv | 11 | 3 years ago | 2 | C++ | ||||||
| Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension | ||||||||||
| Risc V Cpu | 6 | 4 years ago | 1 | Verilog | ||||||
| A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology. | ||||||||||
| Riscv | 5 | 3 years ago | Assembly | |||||||
| RISC-V vector and other assembly code examples | ||||||||||
Alternatives To Riscv V SpecSelect To Compare
Alternative Project Comparisons
Popular Vector Projects
Popular Risc V Projects
Popular Computer Science Categories
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Assembly
Vector
Risc V