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Search results for fpga systemverilog

fpga x
systemverilog x
132 search results found
Sequent ⭐ 10
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
Awesome Eda ⭐ 9
Fpga Blit ⭐ 9
FPGA implementation of the Blit terminal
Fpga Mandelbrot ⭐ 9
A fast, parametrized Mandelbrot generator written in SystemVerilog.
Ultra96 Fractal ⭐ 9
Hardware accelerated Julia set explorer running on Ultra96
Fpga_snark_prover ⭐ 9
An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs
Pito_riscv ⭐ 8
A Barrel design of RV32I
Pic16f Antastic ⭐ 8
A synthesizable picmicro-midrange clone for FPGAs
S Link ⭐ 8
An Open Source Link Protocol and Controller
Fpga_mafia ⭐ 8
Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
Methane ⭐ 8
A polyphonic synthesizer built on fpga and esp32
Peakrdl Verilog ⭐ 8
Generate verilog register file from systemRDL description
Rvc_asap ⭐ 8
riscv-core-as-simple-as-passible
Phi ⭐ 7
Hardware description language that tries not to suck
Hardcloud ⭐ 7
FPGA as an OpenMP Offloading Device.
Axi_to_spi ⭐ 7
Designing means to communicate as an SPI master, being a part of AXI interface
Mapache64 ⭐ 7
Custom 6502 Video Game Console
Fpga Webinar 2020 ⭐ 7
De10lite Hdl ⭐ 7
Verilog for interacting with components of the DE10-Lite board.
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
Mipi Csi 2 ⭐ 6
Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA
Rp32 ⭐ 6
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Apogeorv ⭐ 6
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Vga_interface ⭐ 6
Edapack ⭐ 6
Provides a packaged collection of open source EDA tools
Mips_cpu ⭐ 6
Single Cycle 32 bit MIPS
Upduino Example ⭐ 6
Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation
Usb_pd_monitor ⭐ 5
USB PD cc pin monitor implemented in a Tang Nano 9K FPGA.
Wolv Z0 ⭐ 5
Wolv Z0 is a RISC-V CPU core
Tn_serv ⭐ 5
SERV RISC-V sample for Tang Nano FPGA board
Twn_generator ⭐ 5
Generate an FPGA design for a TWN
Ofd ⭐ 5
Open FPGA Debug core
Polyphonic_fpga_synthesizer ⭐ 5
Polyphonic Synthesizer for FPGA device
Procyon ⭐ 5
Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
Spif ⭐ 5
SpiNNaker peripheral interface
Elektronika Digitalaren Oinarrizko Kontzeptuak ⭐ 5
Curso con FPGA para alumnos de secundaria y bachiller
Virtio Fpga ⭐ 5
A platform for emulating Virtio devices with FPGAs
Risc 16 ⭐ 5
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
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