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Search results for fpga nexys a7

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Vhdl Course ⭐ 58

VHDL course at Brno University of Technology

Scoreboard Wtimer ⭐ 23

Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.

Hastlayer Hardware Framework Xilinx ⭐ 5

Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.

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