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nexys-a7
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4 search results found
Vhdl Course
⭐
58
VHDL course at Brno University of Technology
Scoreboard Wtimer
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23
Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
Fusesoc_template
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10
Example of how to get started with olofk/fusesoc.
Hastlayer Hardware Framework Xilinx
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5
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.
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