Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Vexriscv | 2,135 | 3 months ago | 100 | mit | Assembly | |||||
A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
Neorv32 | 1,337 | 2 months ago | 15 | bsd-3-clause | VHDL | |||||
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
Riscv_vhdl | 552 | 3 months ago | 2 | apache-2.0 | Verilog | |||||
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
Potato | 229 | a year ago | 4 | bsd-3-clause | VHDL | |||||
A simple RISC-V processor for use in FPGA designs. | ||||||||||
Fomu Workshop | 148 | 10 months ago | 65 | apache-2.0 | Verilog | |||||
Support files for participating in a Fomu workshop | ||||||||||
Freezing Spice | 88 | 5 years ago | 2 | bsd-3-clause | VHDL | |||||
A pipelined RISCV implementation in VHDL | ||||||||||
Rpu | 70 | 4 years ago | apache-2.0 | VHDL | ||||||
Basic RISC-V CPU implementation in VHDL. | ||||||||||
Getting Started | 46 | 4 years ago | 25 | Shell | ||||||
List of ideas for getting started with TimVideos projects | ||||||||||
Neorv32 Setups | 44 | 2 months ago | 5 | bsd-3-clause | VHDL | |||||
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains. | ||||||||||
Rudi Rv32i | 41 | 3 years ago | 2 | mit | VHDL | |||||
A rudimental RISCV CPU supporting RV32I instructions, in VHDL |