Potato

A simple RISC-V processor for use in FPGA designs.
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Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
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A FPGA friendly 32 bit RISC-V CPU implementation
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🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Potato229
a year ago4bsd-3-clauseVHDL
A simple RISC-V processor for use in FPGA designs.
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Support files for participating in a Fomu workshop
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A pipelined RISCV implementation in VHDL
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Basic RISC-V CPU implementation in VHDL.
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📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
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A rudimental RISCV CPU supporting RV32I instructions, in VHDL
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