| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
over 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| skordal/potato |
229 |
|
0 |
0 |
over 3 years ago |
0 |
|
4 |
bsd-3-clause |
VHDL |
| A simple RISC-V processor for use in FPGA designs. |
| im-tomu/fomu-workshop |
148 |
|
0 |
0 |
almost 3 years ago |
0 |
|
65 |
apache-2.0 |
Verilog |
| Support files for participating in a Fomu workshop |
| inforichland/freezing-spice |
88 |
|
0 |
0 |
over 7 years ago |
0 |
|
2 |
bsd-3-clause |
VHDL |
| A pipelined RISCV implementation in VHDL |
| Domipheus/RPU |
70 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
apache-2.0 |
VHDL |
| Basic RISC-V CPU implementation in VHDL. |
| timvideos/getting-started |
46 |
|
0 |
0 |
almost 6 years ago |
0 |
|
25 |
|
Shell |
| List of ideas for getting started with TimVideos projects |
| stnolting/neorv32-setups |
44 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
bsd-3-clause |
VHDL |
| 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains. |
| hamsternz/Rudi-RV32I |
41 |
|
0 |
0 |
over 5 years ago |
0 |
|
2 |
mit |
VHDL |
| A rudimental RISCV CPU supporting RV32I instructions, in VHDL |
